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Different assignment polices are applied to exploit the trade-offs between minimizing register usage and avoiding bank conflicts and anti-dependencies. Several extensions are introduced to the traditional graph-coloring algorithm to support variables with different sizes and to accurately model liveness under divergent branches. To manage compilation overhead, our register allocation framework adopts a hybrid approach that separates the assignment of local and global variables. Since compilation occurs in a JIT environment, the allocator also needs to incur little overhead. Not only should the allocator make a program spill-free, but it must also reduce the number of register bank conflicts and anti-dependencies. These distinctive characteristics impose challenges for register allocation, as input programs may have arbitrarily-sized variables, partial updates, and complex control flow.
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Intel GPUs feature a large byte-addressable register file organized into banks, an expressive instruction set that supports variable SIMD-sizes and divergent control flow, and high spill overhead due to relatively long memory latencies. In this paper we present the register allocator in the production compiler for Intel HD and Iris Graphics. Register allocation is a well-studied problem, but surprisingly little work has been published on assigning registers for GPU architectures.